SDI II Intel® FPGA IP Core

Overview

The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

IP Core Feature	Description
Transceiver data interface	20 bit, 40 bit, and 80 bit
Supported SDI standards and video formats	Single Standard Standard Definition or SD-SDI High Definition or HD-SDI 3 gigabits per second (Gbps) or 3G-SDI Dual Link HD-SDI Multiple Standards Dual Standard up to HD-SDI Triple Standard up to 3G-SDI Multi Standard up to 12G-SDI Note: Not all devices support all formats, see “Device Support” below
SMPTE support	SMPTE425M level A support (direct source image formatting) SMPTE425M level B support (dual link mapping)
Other features	Payload identification packet insertion and extraction Clock enable generator Video rate detection Cyclic redundancy check (CRC) encoding and decoding (except SD) Dual link data stream synchronization (only HD)

Block Diagram

Deliverables

Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim*- Intel® FPGA Edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control

Technical Specifications

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SDI II Intel® FPGA IP Core

Overview

Block Diagram

Deliverables

Technical Specifications

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