SATA Host Controller
Overview
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. The LDS SATA HOST STR4GX IP is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable 3Gbs. The LDS SATA HOST STR4GX IP is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of 1.5Gbps speed selection and 75MHz in case of 3Gbs speed selection. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
Key Features
- Rate Match FIFO
- Manage SATA reference frequency difference between the FPGA and the Disk
- Physical Layer features
- Detect and generate OOB sequence
- Detect the K28.5 comma character
- 16 bit parallel output
- Power management mode handled by state machine
- Provides error indication to upper layers
- 8b/10b in ALTERA Stratix IV ALT_GX Macro
- Manages 1.5Gbs or 3Gbs data rate
- Link Layer features
- Scrambling of tx data and descrambling of rx data
- CRC 32 generation and check
- Report transmission status and error to Transport Layer
- Enable BIST loopback and pattern generation modes
- Auto inserted hold primitive to avoid FIFO overflow and underflow
- Partial and slumber power management modes
- The interface between the link layer and the transport layer is 32-bit wide
- Transport Layer features
- 48-bits sector address
- Programmed IO (PIO) and DMA modes
- Support BIST FIS transmission and reception
- Automatic error FIS retry capability
- Implement Shadow Registers and SATA SuperSet registers
- Simple synchronous CPU and DMA Interface for data transfers
- DMA interface to memory space or FIFOs
- Support DMA Abort primitive
Technical Specifications
Maturity
Good
Availability
Now