The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devices. Maximum supported bandwidth is 48 Gbps. The serial link employs multiple high-speed gigabit transceivers.
ARCHITECTURE
This high performance implementation of a SAS Initiator support every mandated feature outlined by the latest SAS Specification. The implementation is highly configurable, to provide the most flexibility and satisfy every need.
The design is cleanly partitioned in to the fundamental function blocks of a SAS Initiator:
- PHY (SERDES)
- PHY Layer
- Port Layer
- Link Layer
- SSP
- SMP
- SATA
- Transport Layer
- AXI Interface
We include a FPGA based PHY, or the IP Core can interface to a standard SAS PHY from a 3rd party. The FPGA based PHY is targeted for Xilinx series 7 devices, with GTX and GTH transceivers.
Our PHY includes all functions required to bring up the link all the way to 12G.
The SoC interface consists of a AXI Light interface to access internal registers, and a AXI 4.0 Streaming interface for data transfers. We have successfully tested this IP Core with the following SAS SSDs:
- HGST 200GB SAS12G SSD
- Seagate 200GB SAS12G SSD
- Toshiba 200GB SAS12G SSD
- Micron 100GB SAS6G SSD
- Talos (OCZ) 200GB SAS6G SS
