The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA. It adds support for the F and D standard extensions, which provide the S54 with double-precision floating-point capabilities.
The S54 is ideal for demanding applications such as avionics, signal processing, and industrial automation.
S54 64-bit embedded RISC V processor
Overview
Key Features
- Fully compliant with the RISC-V ISA specification
- RV64IMAFDC Support
- RV64I - 64-bit RISC-V with 32 integer registers
- Integer Multiplication and Division (M) support
- Atomic (A) extension for high-performance, portable software
- F and D extension for hardware double-precision floating-point
- Compressed (C) extension for better code density
- Machine and User Mode Support
- In-order, 5-6 stage variable pipeline
- Advanced Memory Subsystem
- 16KB, 2-way Instruction Cache
- Instruction Tightly Integrated Memory (ITIM) option
- Up to 64KB Data Tightly Integrated Memory (DTIM) support
- Support for up to 40 physical address bits
- Efficient and Flexible Interrupts
- Local interrupts w/ vectored addresses - up to 16
- Platform Level Interrupt Controller (PLIC) - 255 interrupts w/ 7 priority levels
- RISC-V Core Local Interruptor (CLINT) - 1 timer, 1 SW
- 8-Region Physical Memory Protection (PMP)
- High performance TileLink Interface
- 2.87/1.70 DMIPS/MHz (Best Effort/Legal)
- 3.01 CoreMark/MHz
Block Diagram
Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
Technical Specifications
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