ROM Compiler IP, UMC 55nm eFlash process
Overview
UMC 55nm eFlash Via1 ROM compiler with HVT.
Technical Specifications
Foundry, Node
UMC 55nm eFlash
UMC
Pre-Silicon:
55nm
Related IPs
- SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- SMIC 0.25um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- SMIC 0.13um Low Leakage UHD RVT_x005F_x000D_ Logic standard cell library, compatible with E-Flash and EEPROM process.
- MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
- SMIC 0.13um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- SMIC 0.13um 90% shrunk HVT Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler