RLDRAM3 Synthesizable Transactor provides a smart way to verify the RLDRAM3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's RLDRAM3 Synthesizable Transactor is fully compliant with standard RLDRAM3 Specification and provides the following features.
RLDRAM3 Synthesizable Transactor
Overview
Key Features
- Supports 100% of RLDRAM3 protocol standard
- Supports all the RLDRAM3 commands as per the specs
- Supports the following devices:
- X18
- X36
- Supports SDR addressing
- Supports reduce cycle time (tRC(MIN) = 6.67 - 8ns)
- Supports programmable read/write latency (RL/WL) and burst length
- Supports data mask for write commands
- Supports integrated on-die termination (ODT)
- Supports single or multibank writes
- Supports extended operating range (200-1200MHZ)
- Supports read training register
- Supports multiplexed and non-multiplexed addressing capabilities
- Supports mirror function
- Supports output driver and ODT calibration
- Supports IEEE 1149.1 compliant JTAG boundary scan
- Supports full-timing as well as behavioral versions in one model
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the RLDRAM3 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes