The agileRCOSC is based on a traditional architecture which allows for the frequency to be trimmed to remove the effects of process variation. This can also be configured as a Free Running Clock (FRC) where a high accuracy clock is not required.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
RC Oscillator
Overview
Key Features
- Start-up Time: Typ 10us
- Frequency Range: 20KHz – 100MHz
- Accuracy (Calibrated) Max = ± 5%
- Current Consumption: Typ 100uA @ 10MHz
- Configurable to your specification
- Clean start-up
- Trimmable frequency
- Low power
- Customizable design for simple SoC integration
Benefits
- DFT - Incorporates analog monitor (test) outputs to facilitate ATE test and debug
- On chip clock generator
Block Diagram
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report