Mobiveil's RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The Mobiveil RapidIO Controller Solution can be used as a Host or device. The RapidIO Controller when used along with Mobiveil’s RapidIO to AXI Bridge (RAB) provides speed multi-channel DMA, Data Message and Data streaming functionality to match the bandwidth requirements of the RapidIO interface.
The Mobiveil RapidIO Controller is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The RapidIO solution provides highly scalable bandwidth through a configurable data path width and clock frequency.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
RapidIO Controller with V4.1 Support
Overview
Key Features
- Compliant to RapidIO Specifications revision 4.1
- Compliant with RapidIO Error Management
- Extension specification, Revision 4.1
- Implements Logical, Transport and Physical layers functions
- Architected for high link utilization and low latency
- Efficient receive and transmit buffering scheme
- Implements receiver controlled flow control
- Provides Packet oriented user logic interface
- Serial and Parallel interfaces supported
- 1x, 4x,8x and 16x serial interface and 8 and 16 bits parallel interface
- 64/128/256-bit internal data path
- PBUS interface for configuration register access
- Up to 256 Bytes data payload
- Hardware error recovery
- Exhaustive error reporting and handling
- Pass-Through mode of operation for RIO packets up to 288 bytes
- Accept all Mode of operation for fail over support
Benefits
- Superior architecture-optimized for high performance, link utilization, low latency, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with Mobiveil's UVM VIP
Block Diagram
Applications
- Base Stations
- Storage
- Networking and communications
- General purpose system chip interconnect for any compute platform
Deliverables
- Verilog RTL
- Behavioral test bench and test cases
- RapidIO BFM
- ASIC Synthesis environment
- Documentation
Technical Specifications
Foundry, Node
Technology Independant
Maturity
Gold
Availability
Now
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