HCLTech offers IP POR hcl_por_t40_v1 circuit provides a reset signal to the chip when supply ramps up so that the chip always starts in a known state. It ensures that stable and adequate supply voltages are available to the circuit. The hcl_por_t40_v1 is implemented in a tsmcN40 CMOS process.
If POR CORE circuit fails (stuck at either zero or VDD), then to power up the chip an external bypass signal is needed. Hence an additional dedicated BYPASS block is provided to bypass POR CORE circuit.
Hcl_por_t40_v1 architecture also has a TEST MODE CIRCUITS block which consists of circuits which are used to enable and generate A_TESTOUT from different outputs of POR CORE circuit.
Power On Reset (POR)
Overview
Key Features
- Provides BYPASS mode.
- Minimum Reset delay of 2.782 µs. (at RC-Worst)
- Rising threshold voltage: Maximum of 1.57V(at RC-Worst, RC-Best)
- Falling threshold voltage: Minimum of 1.25V. (at RC-Worst, RC-Best)
- Hysteresis voltage: Minimum of 70mV. (at RC-Worst, RC-Best)
- Brownout detection duration: 11.05 µs. (at RC-Worst corner)
- Quiescent current: Maximum of 11.2 µA.
- Area of 156.2*88.3 sq. µm.
Block Diagram
Applications
- RCOSC,
- DIGITAL CORE,
- Analog IP A(example: RF ADC),
- Analog IP B(example: DAC)
- Default trim + level shifter.
- JTAG
Technical Specifications
Foundry, Node
40 nm TSMC
Availability
Immediate