Power on Reset IP, Input: 1.5V - 3.9V, UMC 55nm SP process
Overview
3.9~1.5V (RTC Core Cell Library operating voltage+), Rise-relax voltage (Vrr), min. 1.6V (1.6V~2.3V) Power On Reset, UMC 55nm SP/RVT Low-K Logic process.
Technical Specifications
Short description
Power on Reset IP, Input: 1.5V - 3.9V, UMC 55nm SP process
Vendor
Vendor Name
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
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