Power on Reset IP, Input: 1.2V, Vrr=Vfr=0.8V, UMC 55nm LP process
Overview
Vrr=Vfr=0.8V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
Technical Specifications
Short description
Power on Reset IP, Input: 1.2V, Vrr=Vfr=0.8V, UMC 55nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 55nm LP
UMC
Pre-Silicon:
55nm