Power on Reset IP, Input: 1.0V/3.3V, UMC 90nm SP process
Overview
Vrr=2V Vfr=1.95V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset, special request by ASAL, UMC 90nm SP/RVT Low-K Logic process.
Technical Specifications
Short description
Power on Reset IP, Input: 1.0V/3.3V, UMC 90nm SP process
Vendor
Vendor Name
Foundry, Node
UMC 90nm SP
UMC
Pre-Silicon:
90nm
SP
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