The power on reset consists of a Schmitt trigger and simple logic for forced reset input, whish is forced asynchronous reset. Output port is setRe, that means it is low to set flip-flop in particular state.
The block is fabricated in TSMC SiGe BiCMOS 0.18 um.
Power on Reset
Overview
Key Features
- TSMC SiGe BiCMOS 0.18 um
- Low current consumption
- Small layout area
- Portable to other technologies (upon request)
Applications
- Power on reset
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
TSMC SiGe BiCMOS 0.18 um
Maturity
Silicon proven
Availability
Now
TSMC
Silicon Proven:
180nm