Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library

Overview

Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library

Technical Specifications

Short description
Power input 3.3V, Comparator , UMC 55nm uLP/HVT Low-K Logic Process Ultra High Density (6T) C60 Core Cell Library
Vendor
Vendor Name
Foundry, Node
UMC 55nm Logic/Mixed_Mode uLP
UMC
Pre-Silicon: 55nm
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Semiconductor IP