PCIE CONTROLLER IIP

Overview

PCIE Controller interface provides full support for the PCIE synchronous serial interface, compatible with PCIE 5.0 specification. Through its PCIE compatibility, it provides a simple interface to a wide range of low-cost devices. PCIE Controller IIP is proven in FPGA environment. The host interface of the PCIE Controller can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses.

PCIE CONTROLLER IIP is supported natively in Verilog and VHDL

Key Features

Compliant with PCIE 1.0/2.0/3.0/4.0/5.0 Specifications
Full PCIE Controller functionality
Supports PIPE interface.
Compatible with Gen1,2,3,4 and 5
Supports the following modes:
- Root Complex
- Endpoint
Supports full LTSSM state machine
Supports Speed and Link Width negotiation
Supports lane polarity inversion detection and correction
Supports lane reversal detection and correction
Supports Up configure and lane-to-lane de-skew
Supports full link speed and width negotiation up to 16 Lanes
Supports up to 32 bits pipe width
Supports Configurable Fixed Pclk/Fixed Data path implementation for Speed switching
Supports data scrambling for Gen 1,2,3,4,5
Configurable timers and timeout
Supports Lane Margining at Receiver
Supports full DL state machines
Check all framing, LCRC, and lane rules
Check all DLLP fields and formatting
Supports Retry Mechanism
Supports Scaled Flow Control
Supports Data Link Feature Exchange
Supports queuing for 8 Virtual Channels with configurable depth
Supports up to 8 Traffic Classes
Supports multi-function
Configurable TC to VC queue mapping
Supports MSI/MSI-X Interrupts
Multiple Requester / Completer applications, including user supplied applications
User interface for direct TLP queuing and receipt
Check all TLPs for correct formation of headers, prefixes, and ECRC
Supports ASPM and Software controlled Power Management
Supports Link Power Management
Supports L1 PM Sub states
Supports vF 10-Bit Tag Requester
Supports enhanced Allocation
Supports emergency Power Reduction State
Supports DMA(optional)
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple interface allows easy connection to microprocessor/microcontroller devices.
Functional safety features (B: No certification, with safety features, in line with the development process).

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The PCIE Controller interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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