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PCIe 4.0 Controller

Overview

The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 4.0 Controller works

The PCIe 4.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 4.0 and 3.1/3.0 specifications, as well as the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

Key Features

  • PCI Express layer
    • Comprises complete PCIe 4.0 interface subsystem with Rambus PCIe 4.0 PHY
    • Compliant with the PCI Express 4.0 and 3.1/3.0, and PIPE (8-, 16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode, Switch port configurations
    • Supports x16, x8, x4, x2, x1 at 16 GT/s, 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
    • Additional optional features include OBFF, TPH, ARI, LTR, IDO, L1 PM substates, etc.
  • User Interface layer
    • 256-bit transmit/receive low-latency user interface
    • User-selectable Transaction/Application Layer clock frequency
    • Sideband signaling for PCIe configuration access, internal status monitoring, debug, and more
    • Optional Transaction Layer bypass

Benefits

  • Internal data path size automatically scales up or down (64-, 256- bits) based on max. link speed and width for reduced gate count and optimal throughput
  • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
  • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
  • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code
  • Ultra-low Transmit and Receive latency (excl. PHY)
  • Smart buffer management on receive side (Rx Stream) and transmit side (merged Replay/Transmit buffer) enables lower memory footprint
  • Advanced Reliability, Availability, Serviceability (RAS) features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
  • Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
  • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

Block Diagram

PCIe 4.0 Controller Block Diagram

Applications

  • HPC,
  • Cloud Computing,
  • AI,
  • Machine Learning,
  • Enterprise,
  • Networking,
  • Automotive,
  • AR/VR,
  • Test and Measurement

Deliverables

  • IP files
    • Verilog RTL source code
    • Libraries for functional simulation
    • Configuration assistant GUI
  • Documentation
  • PCI Express Bus Functional Model
    • Encrypted Simulation libraries
  • Software
    • PCI Express Windows x64 and Linux x64 device drivers
    • PCIe C API
  • Reference Designs
    • Synthesizable Verilog RTL source code
    • Simulation environment and test scripts
    • Synthesis project & DC constraint files (ASIC)
    • Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)

Technical Specifications

Foundry, Node
Any
Maturity
In production
Availability
Available
Request Info

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