PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP

Overview

PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP. With compatibility for PIPE 4.3 interface spec, this complies with PCIe Rev3 Base Specification. 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, all three are supported by the output data rate (serial), which has a 25Mhz input clock frequency. 2.5, 5, and 8 gigabits per second. A minimum of 10 Pads and a maximum clock speed of 500MHz are needed. Range of operating voltages: - 2.97V-3.63V, typical =3.3V; 0.99V-1.21V, usual = 1.1V;

Key Features

Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
Supports 5.0Gbps and 10Gbps serial data transmission rate Supports 16-bit or 32-bit parallel interface Data and clock recovery from serial stream
Support 8b/10b encoder/decoder(5Gbps), 128/130 encoder/decoder(BGbps) and error indication
Tunable receiver detection to detect worse case cables
Beacon transmission and reception
Support SSCG function to reduce EMI effects with tunable down-spread amplitude
Selectable TX margining, TX de-emphasis and signal swing values
Built-in-self-test with internal Loopback test option
Programmable analog circuit parameter adjustment and internal test control
Compliant with PCIe Rev3 base specification
Silicon Proven in TSMC 40LP

Benefits

Low Area
Low Power
Compliant with PCIe® 3.1, 2.1, 1.1, and PIPE specifications
PCIe PHY functionality is fully verified

Applications

Notebooks
Smartphones
Tablets
Embedded mobile computing
Ultraportable laptops
Automotive
Mobile multimedia
Digital home
Digital office
Wireless connectivity

Deliverables

Application Note / User Manual
Behavior model, and protected RTL codes
Protected Post layout netlist and Standard Delay Format (SDF)
Synopsys library (LIB)
Frame view (LEF)
Metal GDS (GDSII)
Test patterns and Test Documentation

Technical Specifications

Foundry, Node

TSMC 40LP

Maturity

In Production

Availability

Immediate

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