Motorola MC6845 Functional Equivalent CRT Controller

Overview

The DB6845 CRT Controller core is a full function equivalent to the Motorola MC6845 device. The DB6845 interfaces a microprocessor to a raster-scan CRT display. The microprocessor access 19 registers (1 Address and 18 Data Registers) within the DB6845 in order to provide video timing, refresh memory addresses, cursor, and light pen strobe signals. CRT video timing signals include Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) output signals. Refresh memory addressing includes Memory Address (MA[13:0]) and Row Address (RA[4:0]) output buses.

Key Features

Synchronous, synthesizable VHDL Core, functionally equivalent to Motorola MC6845.
Capable of driving alphanumeric, semi-graphic, or bit-mapped graphics displays. Wide range of programmable screen formats.
Programmable registers controlling output signals Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) signals. Programmable horizontal line rate and sync pulse width. Programmable vertical frame rate.
Programmable registers controlling Memory Address (MA[13:0]) start address. Programmable Start Address Register for Hardware Scrolling.
Programmable registers controlling Row Address (RA[4:0]) size, yielding a character row.
Programmable register controlling Normal Sync (Non-Interlace), Interlace Sync, or Interlace Sync & Video Mode.
Programmable registers for control and format of Cursor.
Light Pen Register.
Microprocessor 8-bit Data Bus and Control Interface.

Block Diagram

Deliverables

The DB9000AXI-DCI is available in synthesizable RTL Verilog, along with a simulation test bench with expected results, datasheet, and user manual.

Technical Specifications

Foundry, Node

IBM, LSI. TMSC, UMC, Tower

Maturity

Successful in Company FPGA Kit Demo Reference Design, Customer Products

Availability

Immediately

TSMC

In Production: 28nm HP , 40nm G , 55nm GP
Pre-Silicon: 28nm HP , 40nm G , 55nm GP
Silicon Proven: 28nm HP , 40nm G , 55nm GP

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