The Digital Blocks DB8259S Programmable Interrupt Controller IP core is a full function equivalent to the Intel Intel 8259A / Intersil 82C59A / NEC uPD8259A devices, with the update to a synchronous design.
The DB8259S RTL Verilog / VHDL outputs were compared to the Intel 8259A device on a cycle-by-cycle basis as captured & represented by the Digital Blocks testbench suite.
The DB8259S Interrupt Controller manages up to eight vectored priority interrupts for a microprocessor. Using multiple instantiations of the DB8259S core and programming it to cascade mode enables up to sixty-four vectored priority interrupts. More than sixty-four vectored interrupts can be accomplished by programming the DB8259S core to Poll Command Mode. Interrupt sources may be either edge or level triggered.
Programmable Interrupt Controller (Synchronous)
Overview
Key Features
- An all synchronous design.
- MCS-80/85 and 8088/8086 processor modes.
- Fully Nested Mode and Special Fully Nested Mode.
- Special Mask Mode.
- Buffered Mode.
- Poll Command Mode.
- Cascade Mode with Master or Slave selection.
- Automatic End-of-Interrupt Mode.
- Specific and Non-Specific End-of-Interrupt Commands.
- Automatic Rotation.
- Specific Rotation.
- Edge and level triggered interrupt input modes.
- Reading of Interrupt Request Register (IRR) and In-Service Register (ISR) through data bus.
- Writing and reading of Interrupt Mask Register (IMR) through data bus.
Benefits
- The DB8259S Synchronous Programmable Interrupt Controller is a silicon-proven interrupt controller IP core. Customers can work off the large industry knowledge surrounding the Intel 8259A and Harris / Intersil 82C59A devices to get microprocessor system designs with interrupt controller requirements up and running quickly.
- The CLK and CLKEN inputs facilitate an all synchronous design. All digital logic is clocked with CLK, enabling integration into FPGA and ASIC synchronous design flows. CLKEN facilitates system data bus connectivity to the microprocessor, and is typically connected to a wait state logic output signal. For fast system bus applications, CLKEN can be not used by tying to its active (or always enabled) VCC level.
Deliverables
- VHDL or Verilog RTL Source.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation Guide.
- Technical Reference Manual.
Technical Specifications
Foundry, Node
IBM, LSI. TMSC, UMC, Tower
Maturity
Successful in Customer designs
Availability
Immediately