Programmable Peripheral Interface

Overview

The Digital Blocks DB8255A Programmable Peripheral Interface IP core is a full function equivalent to the Intel 8255A / 82C55A and Harris / Intersil 82C55A devices.

The DB8255A RTL Verilog / VHDL outputs were compared to the Intel 8255A device on a cycle-by-cycle basis as captured & represented by the Digital Blocks testbench suite.

The DB8255A implements a general-purpose I/O interface connecting peripheral equipment to a microprocessor system bus. The core generates 24 programmable I/O lines which are individually programmed in 2 groups of 12 and used in 3 major modes of operation.

Key Features

24 programmable I/O lines.
8-bit bidirectional data bus with standard microprocessor interface controls.
Three Modes of operation:
Mode 0: Basic Input/Output:
2 groups of 12 I/O lines may be programmed in sets of 4 and 8 to be inputs or outputs.
Mode 1: Strobed Input/Output:
Each group may be programmed to have 8 lines of input or output.
The 3 of the remaining 4 lines are used for handshaking and interrupt control signals.
Mode 2: Bidirectional Bus
Single 8-bit bidirectional bus for both transmitting and receiving data.
Control Word Read-Back Capability.
Direct Bit Set/Reset Capability.
RESET input clears the Control Register and all 24 programmable I/O lines set to input mode.
Available in VHDL.

Benefits

The DB8255A Programmable Peripheral Interface is a silicon-proven 24 line programmable I/O interface IP core. Customers can work off the large industry knowledge surrounding the Intel 8255A / 82C55A and Harris / Intersil 82C55A devices to get microprocessor system designs with programmable I/O requirements up and running quickly.

Deliverables

VHDL Source.
Comprehensive testbench suite with expected results.
Synthesis scripts.
Installation Guide
Technical Reference Manual

Technical Specifications

Foundry, Node

IBM, LSI. TMSC, UMC, Tower

Maturity

Successful in Customer designs

Availability

Immediately

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