MIPI TWP Synthesizable Transactor

Overview

Key Features

• Compliant with MIPI TWP version 2.0 specification.
• Full MIPI Debug functionality.
• Supports all Debug CCC's and Opcodes
• Supports following three layer
• Layer T1: Flow Control. Supported by the TWP Padding Packet.
• Layer T2: Alignment Synchronization. Supported by the TWP Frame Synchronization Packet.
• Layer T3: Data. Supported by the TWP Frame
• Allows up to 111 source trace streams to be represented as a single stream and later separated by either hardware or software.
• Supports Error handling and flushing mechanism
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices
• Supports on-the-fly protocol and data checking
• Ability to transmit strings to help verification of SOC
• Notifies the test bench of significant events such as transactions, warnings, and protocol violations
• MIPI TWP Synthesizable VIP comes with complete test suite to verify each and every feature of MIPI TWP specification
• Status counters for various events in bus

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the MIPI TWP testcases
• Examples showing how to connect various components, and usage of Synthesiable VIP
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications