IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI M-PHY IP > MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+

MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+

Overview

The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification are all supported by the MIPI M-PHY Gear 4 IP. a high-bandwidth serial interface technology that can support HS Gear4 rates of up to 11.6Gbps and was specifically designed for mobile applications to achieve reduced pin count and excellent battery efficiency. The UniPro controller and UFS Controller are supported by the RMMI interface compatible MIPI M-PHY Gear 4 IP. The MIPI M-PHY offers reliable embedded system debugging and receiver ocular data monitoring using low-cost Build-In-Self-Test (BIST).

Key Features

  • Compatible with PCIe base Specification
  • Full compatible with PIPE3.0 interface specification
  • Independent channel power down control
  • Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
  • Support 16-bit/32bit parallel interface
  • Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and Deemphasis
  • Support TX detect RX function in PCIe Mode
  • Support Beacon signal generation and detection in
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Embedded Primary & Secondary ESD Protection
  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
  • Silicon Proven in TSMC 28nm HPC+

Benefits

  • RX:DFE+CTLE, TX:2-tap FFE
  • Max. Channel Loss:~14dB @6GHz Nyquist
  • Low operation current and low standby current
  • Competitive IP PPA leading in the market

Block Diagram

MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 28 HPC+ Block Diagram

Deliverables

  • Application Note / User Manual
  • Behaviour model, and protected RTL codes
  • Protected Post layout netlist and Standard Delay Format (SDF)
  • Library (LIB)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Technical Specifications

Foundry, Node
TSMC 28HPC+
Maturity
In Production
Availability
Immediate
TSMC
In Production: 28nm HPCP
Request Info

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