MIPI M-PHY in TSMC 65LP

Overview

The MXL-M-PHY-DIGRF is a high-frequency low-power, low-cost, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY and DigRF. The IP can be used as a physical layer for the Baseband to RFIC interface. It supports the DigRF v4 standard.
By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained.
Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. The core employs Mixel’s Logarithmic approach, enabling efficient implementation of multiple configurations.

Key Features

Supports the MIPI Standard for M-PHY, Draft Specification v0.90.00-r02 and DigRF v4 V1.10.00.0.04
Dual-simplex point-to-point interface with ultra low voltage differential signaling
Slew-rate control for EMI reduction
Supports HS mode (GEAR 1-2, A & B)
Supports LS mode (Sys-Burst)
1.25-3Gbps data rate in HS mode
19.2-52Mbps data rate in LS mode
Suitable for copper and optical media
Mixel’s Logarithmic approach efficiently supports large number of different configurations
Low power dissipation

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive
Storage

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 65LP

Maturity

Upon Request

Availability

Now

TSMC

Silicon Proven: 65nm LP

Request Info