MIPI DPHY Receiver on GF55LPe
Overview
This IP supports operational data rates 80Mbps to 1.5Gbps per One lane for HS mode, and up to 10Mbps for LP modes transfer rates.
Key Features
- MIPI D-PHY version 1.2 compliant PHY receiver
- Consists of 4 data lane and 1 clock lane
- Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps)
- Integrated control interface logic to supports PHY Protocol Interface (PPI)
- Integrated 100-ohm termination resistors with common-mode biasing
- Configurable analog characteristics
- Timing skew
- Terminator resistance
- BGR voltage
- 1.2V power supply
- Support GlobalFoundry 55nm LPe process
Block Diagram
Deliverables
- Verilog RTL or netlist source code of lane control unit
- Liberty timing models for synthesis and STA
- Timing constrains for synthesis and physical layout
- Verilog behavior model of PHY part
- Physical design database
- Integration guidelines
Technical Specifications
Foundry, Node
GF, 55nm LPe
Maturity
in development
Availability
Design kit ready
GLOBALFOUNDRIES
Pre-Silicon:
55nm
Related IPs
- MIPI D-PHY in ON Semiconductor 180nm
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Camera MIPI D-PHY Receiver 4.5Gbps 4-Lane
- Camera MIPI D-PHY v1-1 1.5Gbps / sub-LVDS combo Receiver 4-Lane
- MIPI CSI-2 Receiver
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)