MIPI D-PHY Receiver for CSI-2 of TSMC 40nm LP
Overview
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process.
Key Features
- Renesas MIPI D-PHY Receiver can be used for analog Receiver of following interface.
- MIPI alliance Specification for D-PHY Version 2.1 15 December 2016.
- MIPI alliance Specification for Camera Serial Interface 2 (CSI-2) Version 2.0 7 Dec 2016.
- Technology is TSMC 40nm LP 1p8M (4x2y1z).
- Supply voltage can be applied 1.18V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 1.0Gbps at High-speed mode.
Block Diagram
Technical Specifications
TSMC
Pre-Silicon:
40nm
LP
Related IPs
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI CSI-2 Receiver
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY