MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP

Overview

The MXL-DPHY-CSI-2-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1.
The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in system testing while minimizing area and leakage power.

Key Features

Supports MIPI Alliance Specification for D-PHY Version 2.1
Consists of 1 Clock lane and 4 Data lanes
Embedded, high performance, and highly programmable PLL
Supports both low-power mode and high speed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane in high speed D-PHY mode
10 Mbps data rate in low-power mode
Low power dissipation
Testability support including internal loopback

Benefits

The MIPI D-PHY TX+ is a Mixel proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (DSI) Transceiver. It is optimized to achieve full-speed production testing, in-system testing, and higher performance compared to traditional configurations, while reducing area and standby power.

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC 40ULP

Maturity

Silicon Proven

Availability

Now

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