MIPI D-PHY CSI-2 TX (Transmitter) 2.5Gbps in TSMC 65LP

Overview

The MXL-DPHY-2p5G-CSI-2-TX-T-65LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.

Key Features

Supports MIPI Alliance Specification for D-PHY Version 2.1
Consists of 1 Clock lane and 2 Data lanes
Embedded, high performance, and highly programmable PLL
Supports both low-power mode and high speed mode with integrated SERDES
80 Mbps to 1.5 Gbps data rate per lane without Deskew calibration
2.5 Gbps data rate per lane with skew calibration in high speed D-PHY mode
10 Mbps data rate in low-power mode
Low power dissipation
Testability support

Benefits

Area optimized MIPI IP for MIPI CSI-2 TX.

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 65LP

Maturity

Upon Request

Availability

Now

Request Info