MIPI CSI-2 V4 Host Controller ASIL Compliant

Overview

The MIPI CSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all protocol functions defined in the MIPI CSI-2 specification. The IP solutions provide high-speed serial interface between an application or image processor and image sensors. The CSI-2 Host and Device Controllers can be configured to handle up to 8 data lanes or 3 trios and can support data transfers from 80 Mb/s in low-power mode to 3.5Gs/s per trio and 4.5Gbps per lane. The controllers handle all packet encoding and support all CSI-2 specified data formats including: general frame or digital interlaced video with or without accurate sync timing and virtual channel interleaving. The CSI-2 Host and Device Controllers support wide PHY Protocol Interface (PPI) for reliable high-speed data transfer. The controllers are ASIL B Ready ISO 26262 certified, meeting the stringent requirements of automotive functional safety applications.

The MIPI CSI-2 Host and Device Controllers, I3C Controller, C-PHY/D-PHY, and D-PHY provide a complete camera interface IP solution that enables designers to lower their risk and cost of integrating the MIPI CSI-2 interface into image sensors, application processors, bridge integrated circuits (ICs) and multimedia coprocessors, while improving time-to-market.

Key Features

  • Supports key features of the latest MIPI CSI-2 specification
  • PPI interface to MIPI C-PHY v1.2 and D-PHY v2.1
    • Configurable up to 8 data lanes or 4lanes/3 trios
  • Programmable multi-lane merging
  • Short and long packet format and all primary and secondary CSI-2 data formats
  • Extended virtual channels and RAW data types
  • Detection of low-power (LP) and ultra low-power (ULP) modes
  • Error detection and correction with interrupt at PHY, packet, line and frame level
  • ASIL B Ready ISO 26262 certified
  • Arm® AMBA® APB™ control and configuration

Block Diagram

MIPI CSI-2 V4 Host Controller ASIL Compliant Block Diagram

Technical Specifications

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Semiconductor IP