MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor.
MIPI CSI-2 Receiver for FPGA
Overview
Key Features
- Realize MIPI I/F with Low cost
- Series development for small quantity, large variety
- Available for evaluation of Product development
- Data Lane 1~4Lane
- Bit Rate Max 1.5Gbps/Lane
- Data Formats Raw8/10/12/14?RGB565/666/888?YUV422(8/10bit)etc
Block Diagram
Applications
- Automotive
- Communications Consumer Electronics
Deliverables
- RTL:Verilog-HDL
- Functional specification sheet
- Design specification sheet
- Verification environment(sample pattern)
Technical Specifications
Availability
We also accept customization according to customer needs.
Related IPs
- MIPI CSI-2 V3 RECEIVER INTERFACE IP
- MIPI CSI-2 Controller Core
- MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Receiver v1.1 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
- MIPI CSI2 Receiver