MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor.
MIPI CSI-2 Receiver for FPGA
Overview
Key Features
- Realize MIPI I/F with Low cost
- Series development for small quantity, large variety
- Available for evaluation of Product development
- Data Lane 1~4Lane
- Bit Rate Max 1.5Gbps/Lane
- Data Formats Raw8/10/12/14?RGB565/666/888?YUV422(8/10bit)etc
Block Diagram
Applications
- Automotive
- Communications Consumer Electronics
Deliverables
- RTL:Verilog-HDL
- Functional specification sheet
- Design specification sheet
- Verification environment(sample pattern)
Technical Specifications
Availability
We also accept customization according to customer needs.
Related IPs
- MIPI CSI-2 Receiver
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- MIPI D-PHY CSI-2 RX (Receiver) IP
- High Performance Second Generation Extended MIPI CSI2 Receiver
- Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock