IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI C-PHY/D-PHY Combo IP > MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)

MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)

Overview

Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for FinFET processes and compliant with the MIPI C-PHY and D-PHY specifications, operates at 6.5Gb/s per lane and 6.5Gs/s per trio respectively for a maximum speed of 44.5Gb/s. The Synopsys C-PHY/D-PHY addresses energy requirements by supporting low-power state modes and delivering below 1.2pJ/ bit at the maximum speed. The PHY offers built-in test capabilities, including pattern generator, logic analyzer, and loopback modes covering all circuits. The Synopsys C-PHY/D-PHY IP interoperates with Synopsys’ ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications.

Key Features

  • Compliant with the latest MIPI C-PHY and D-PHY specifications
  • Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
  • D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
  • C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
  • Multiple low-power modes, including shut-down, provides multiple test modes for increased reliability
  • Easy integration with the protocol controller layer by implementing the MIPI recommended PPI
  • Reliable, high-speed interface for camera and display applications, reducing line count and minimizing cable wires and EMI shielding requirements

Benefits

  • Compliant with the MIPI D-PHY specification, v2.1
  • 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
  • Compliant with the MIPI C-PHY specification, v2.0
  • 3 trios in C-PHY mode up to 6.5Gs/s per trio
  • Aggregate throughput up to 44.5Gb/s in C-PHY mode and 26Gb/s in D-PHY mode
  • Wide PHY Protocol Interface (PPI)
  • Low-power escape modes and ultra low- power state modes
  • Shutdown mode
  • High speed BIST and at-speed scan test
  • Primary, secondary, TX- and RX-only configurations
  • Flexible input clock reference and lane/trio swap
  • Silicon-proven, robust design available in advanced process technologies

Applications

  • CSI-2 Host
  • DSI/DSI-2 Host
  • CSI-2 Device
  • DSI/DSI-2 Device

Deliverables

  • Databook
  • Behavioral model
  • LEF file
  • LIB file
  • GDSII Layout Database

Technical Specifications

Foundry, Node
TSMC 16nm, 12nm, N7, N6, N5, N3P - FFC, FF, PFF
Availability
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TSMC
Pre-Silicon: 3nm , 5nm , 6nm , 7nm , 16nm
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