MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 16 FFC

Overview

Low power and cost C-PHY/D-PHY Combo in multiple process nodes. Users can configure this Combo PHY in either D-PHY or C-PHY mode to support a variety of applications. Additionally, it complies with the PPI interface, making it simple to integrate with either the CIS-2 or DSI controller. D-PHY and C/D-PHY Combo have the most competitive PPA (Performance, Power, and Area) and standard compliances in many processes throughout foundries. Along with a wide range of features, the MIPI D-PHY already possesses ISO 26262 ASIL-B certification for automotive multimedia applications.

Key Features

Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
Support both MIPI DSI and CSI-2 protocols
Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
Support LS data rate of 10Mbps and Ultra-low power mode
Support fast lane turnaround (FTA) and alternate low-power (ALP) mode
Support D-PHY mode with 1 clock lane & up to 4 data lanes
Support C-PHY mode up to 3 trios for TX and 4 trios for RX
Support TX-EQ and Rx-EQ function to compensate loss of a long channel
Support additional D-PHY RX mode with 2 sets of (1 clock lane and up to 2 data lanes)
Support additional C-PHY RX mode with 2 sets of 2 trios
Provide D-PHY clock and data lane swap function
Provide C-PHY trios swap function
Provide a stand-alone at-speed multi-lanes (trios) parallel BIST module for mass production tests
Silicon proven in TSMC 16FFC

Block Diagram

Deliverables

GDSII & layer map
Place-Route views (.LEF)
Liberty library (.lib)
Verilog behaviour model
Netlist & SDF timing
Layout guidelines, application notes
LVS/DRC verification reports

Technical Specifications

Maturity

In Production

Availability

Immediate

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