LPDDR5X/5/4X/4 PHY & Controller

Overview

The DDR IP Mixed-Signal LPDDR5X/5/4X/4 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low-power and high-speed applications with robust timing and small silicon area. It supports all JEDEC LPDDR5X/5/4X/4 SDRAM components in the market. The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

The comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.

Key Features

  • rates from 200Mbps to
    • 9600Mbps (LPDDR5X)
    • 6400Mbps (LPDDR5)
    • 4266Mbps (LPDDR4X/4)
  • Compliant with JESD209-5 (LPDDR5X/5) and JESD209-4 (LPDDR4X/4)
  • x16/x32/x64 data bus width extendable
  • Supports LPDDR4X 0.6V IO voltage and LPDDR5 0.5V/0.3V IO voltage
  • Supports LPDDR5 WCK mode, Data copy, Write X and Link ECC features
  • Independent read and write timing adjustments with auto calibration
  • Programmable write post-amble (0.5 tCK or 1.5 tCK)
  • Supports both PoP and discrete memory package
  • Supports various low power modes, supports DFS and retention modes
  • Supports point to point memory sub-systems and multi-rank
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion, PAD and internal loopback modes
  • Various power-down modes for low power including self-refresh support
  • Low jitter with superior noise rejection
  • APB Port register access interface
  • Supports both wire-bond and flip-chip packaging
  • Wire-bond speed is package limited

Benefits

  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Extensive EDA tool support for various design and automation flow
  • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
  • Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing

Block Diagram

LPDDR5X/5/4X/4 PHY & Controller Block Diagram

Deliverables

  • Extensive documentation
  • Models
  • LIB
  • LEF
  • Place-and-route abstracts
  • LVS netlist
  • GDSII files

Technical Specifications

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Semiconductor IP