LPDDR4x/5 Secondary/Slave (memory side!) PHY

Overview

This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/LPDDR5 combo IP provides the unique opportunity to transmit data between a variety of devices such as AI coprocessors, in-memory compute solutions and emerging memory products.

This is a memory side (Slave-side) interface for AI processors and other ASICS seeking the latest high speed, low power LPDDR interface protocols for general purpose data transfer, while adhering to the well known and well defined LPDDR4X and LPDDR5 standard as specified by JEDEC.

This IP is designed for 7nm TSMC but can be ported to other logic processes. It is also suitable for a wide variety of memories such as DRAM, SRAM as well as emerging memories including non-volatile memories, with appropriate modifications.

Key Features

JEDEC standard LPDDR5 @ 6400 Mb per second per pin.
JEDEC standard LPDDR4X @ 4267 Mb per second per pin.
Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
Support for byte-mode DRAM devices for high capacity systems
ZQ Calibration
Command Bus Training
VREF(CA/DQ) Training
WCK-to-CK Training
Duty Cycle Adjust/Monitor Training

Benefits

Simultaneously supports JEDEC standard LPDDR5, LPDDR4X
Secondary/memory side PHY
Custom implementations available

Applications

Artificial Intelligence Coprocessors
In-Memory Computing
Emerging Memory Products desiring DRAM standard compatibility
General purpose low power high bandwidth data communication

Deliverables

Hard IP

Technical Specifications

Foundry, Node

TSMC n7, portable

Maturity

Available on request

Availability

Available

TSMC

Pre-Silicon: 7nm

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