LPC Synthesizable Transactor provides an smart way to verify the LPC component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPC Synthesizable Transactor is fully compliant with standard LPC Specification and provides the following features.
LPC Synthesizable Transactor
Overview
Key Features
- Compliant to LPC 1.1 specifications.
- Supports bandwidth up to 33 MHz.
- Supports the following operations
- Memory read and write
- I/O read and write
- DMA read and write
- Bus Master memory read and write
- Bus Master I/O read and write
- Firmware memory read and write
- Host is capable of generating all types of LPC transactions.
- Peripheral is capable of responding to all types of LPC transactions.
- Supports variable number of wait states
- Supports Wakeup and Power state transactions.
- Supports insertion of various types of errors.
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations
- LPC Synthesizable Transactor comes with complete test suite to verify each and every feature of LPC specification
- Status counters for various events in bus
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the LPC testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
Technical Specifications
Short description
LPC Synthesizable Transactor
Vendor
Vendor Name