LPC Assertion IP provides an efficient and smart way to verify the LPC designs quickly without a testbench. The SmartDV's LPC Assertion IP is fully compliant with standard LPC Specification and provides the following features.
LPC Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
LPC Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.