Low Power RISCV CPU IP
Key Features
- RISC-V RV32 instruction set:
- I > full support
- M > partial support
- C > full support
- Machine mode only
- 32 vectorized interrupts
- Standard debug as defined per RISC-V
Technical Specifications
Related IPs
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- AHB Low Power Subsystem - ARM Cortex M0
- OSC Crystal Oscillator Low Power Series
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
- Ultra Compact 32-bit RISC-V CPU Core
- Low Power PLL for TSMC 40nm ULP