Low (Leakage) Power Memory
Overview
The low power embedded SP SRAM is specifically architected and designed with mobile and IoT applications in mind that demands the lowest leakage power for maximum battery life.
Key Features
- 55% lower standby leakage power
- 6% lower active power (at same memory access speed)
- 10% smaller in size
- Supports Retention and Power Down modes, with 35% lower leakage in Retention mode
- Synchronous interface
Deliverables
- Design Kit & Tape Kit:
- Verilog Model and Synopsys Model
- LVS netlist (CDL format)
- GDSII layout file (GDSII format)
- LEF view and Antenna LEF view
- Antenna CLF model and Mbist model
- Memory Compiler Manual and Document
Technical Specifications
SMIC
Silicon Proven:
55nm
LL
Related IPs
- Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- AHB Low Power Subsystem - ARM Cortex M0
- OSC Crystal Oscillator Low Power Series
- Low Power PLL for TSMC 40nm ULP