Low Drop-Out Linear Regulator

Overview

The agileLDO is a linear Low Drop-Out voltage regulator (LDO) providing precision and programmable voltage regulation. The regulator architecture provides a high dynamic performance making it suitable for demanding digital applications. Whilst the low noise and high PSRR lends itself to powering noise-sensitive analog circuits. We have a selection of LDOs, with both capless and externally biased options, supporting a wide range of input voltage, output voltage, and output current.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key Features

  • Input Voltage Range: PDK VddIO
  • Programmable Output Voltage Range
  • Current Load: <1mA to 100mA
  • PSRR
  • @DC Typ: 40dB
  • @1MHz Typ: 20dB
  • Load Regulation: Typ 0.3 %/V
  • Line Regulation: Typ 50mV/A
  • Quiescent current (Iq): Typ 100uA
  • Customizable design for simple SoC integration
  • Integrated Test Mode

Benefits

  • Performance: Low noise and high PSRR for noise-sensitive analog circuits Sense input
  •  Low noise and high PSRR for noise-sensitive analog circuits

Block Diagram

Low Drop-Out Linear Regulator Block Diagram

Applications

  • IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

  • Datasheet
  • Testing and Integration Guide
  • Verilog Models
  • Floorplan (LEF)
  • Timing models (LIB)
  • Netlist (CDL)
  • Layout (GDS)
  • Physical Verification Report
  • Design Report

Technical Specifications

Foundry, Node
GlobalFoundries
Maturity
Available on request
Availability
Now
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Semiconductor IP