1-VIA’s VSCOM4L400ALDO0V6 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulation across a wide range of input and output voltages (610-750mV, 8 configurations with 20mV trimmability in each configuration) implemented in TSMC12/16nm CMOS FinFET technology.
The regulator architecture provides high Power Supply Rejection (PSR) and low noise making it suitable for analog and RF applications.
Linear Low-Dropout Regulator (Output Voltage 0.6V)
Overview
Block Diagram
Applications
- Artificial Intelligence (AI)
- Internet of Things (IoT)
- Medical
- Analogue-to-Digital Converter (ADC)
- RF ASICs
- Automotive
- Wireless
- Digital-to-Analog Converter (DAC)
- Mixed-signal ASICs
- SoCs
Deliverables
- Datasheet
- Characterization report
- Layout view (GDSII)
- Abstract view (LEF)
- Behavioural model (VerilogA)
- Integration guidelines and support
Technical Specifications
Foundry, Node
TSMC12/16nm CMOS FinFET
TSMC
Pre-Silicon:
12nm
,
16nm