Library of LVDS IOs cells for TSMC 40G

Overview

The nSIO2000_TS40G_2V5_0V9 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/0.9V or 1.8V/0.9V, designed on the TSMC 40 G technology. The library is composed according to the customer’s choice of cells.

Key Features

TSMC 40 G
2.5V/0.9V IO/Core transistors
Fully compliant with TIA/EIA-644-A-2001
Built-in, low parasitic ESD protection
Easily integrates with TSMC I/O library cells
All-in-ringR topology, so no core silicon area is used by LVDS
The same cells operate with 2.5V/0.9V or 1.8V/0.9V power supplies
Standby/power down mode
Digital loopback functions to ease ATE testing
Up to 2 Gbps data rate LVDS

Applications

Multi-purpose reconfigurable IO
Point-to-point, point-to-multipoint or bus-based IC high-speed data communications
Intra-package (e.g. MCM or SIP) inter-die high-speed data communications
Backplane high-speed data communications
High-speed serial communications (HDMI, SATA, PCIeX, etc.)
Communication to LCD/OLED screens
Video sensor digital data interface

Deliverables

GDS II layouts
LEF abstracts
CDL netlists
Liberty timings
Verilog description
A full datasheet
An integration note

Technical Specifications

Foundry, Node

TSMC 40 G

Maturity

Silicon proven

TSMC

Silicon Proven: 40nm G

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