This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. LVDS transmitter I/O can obtain good impedance matching by setting internal terminal impedance enable. There are multi-bits controlling signals to get different differential output swings and common mode voltage.
LVDS receiver I/O can receive differential signals with full-scale common voltage and small differential voltage.
Library of LVDS Ios cells in TSMC 180nm~22nm
Overview
Key Features
- ? Conforms to the TIA/EIA-644-A LVDS standard
- ? Suitable for vertical placement
- ? Data rate up to 1.2Gbps
- ? Simple method for testing LVDS transmitter and receiver
- ? 4-bit controlling signals to get different differential output swings
- ? 4-bit controlling signals to get different common voltage
- ? LVDS receiver receives differential signals with full-scale common voltage and small differential voltage
- ? Operating temperature range: -40°C ~ +125°C
Applications
- SoC Interconnection
- Display,Video
Technical Specifications
Maturity
Available on request
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