LVDS IP
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220
LVDS IP
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LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
- The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
- A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link.
- The polarity of differential signals for each data lane can be controlled.
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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Process: Silterra 0.16um CMOS 1P5M Process
- Supply Voltage Range: AVDD33 = 3.3v +/-10%, AVDD18 = 1.8v +/-10%
- Ambient Temperature: 0°C~80°C
- Compatible with BLVDS_25 of Spartan-3A FPGA
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MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
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MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- Combo PHY for both MIPI D-PHY CSI-2 RX and LVDS
- TSMC 28HPC+
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MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
- The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
- A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
- The polarity of differential signals for each data lane can be controlled.
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Four Channel (4CH) LVDS in TSMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 175 Mbps - 1000 Mbps bandwidth/channel
- Up to 4 Gbps data throughput
- 7-bit/10-bit serial data transmitted per pixel clock per channel
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Four Channel (4CH) LVDS Receiver in TSMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- Consists of 1 Clock lane and up to 4 Data lanes
- Up to 1.0 Gbps bandwidth per channel
- Up to 4.0 Gbps data throughput
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MIPI D-PHY CSI-2 TX (Transmitter) in TowerJazz 65BSB
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
- 80 Mbps to 1.2 Gbps data rate per lane in high-speed D-PHY mode
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Library of LVDS IOs cells for TSMC 65LP
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
