LDPC Encoder/Decoder for Flash controller

Overview

Key Features

• Strong error correction performance
• Supporting wide range of data-rates from 0.83 to 0.95
• No error floor @UBER=10E-15
• High throughput with low complexity hardware
• Hard decision and multi-bits soft decoding support
• Error bits number output when decodable
• Original frame output when un-decodable
• Early termination technique

Benefits

• New software tools:
• Ultra-low error floor LDPC code construction tool
• Error floor estimation tool

Applications

• Flash controller error correction

Deliverables

• Source Code for Matlab simulation and matrix information
• Source Code for fast simulation on Nvidia GPU
• Verilog HDL Source Code for En/Decoder IP
• IP Verification Environment
• FPGA Verification Environment Reference Design
• IP User Guide
• IP Test Documantation
• Integration support including consulting
• Ultra-low error floor LDPC code construction tool
• Error floor estimation tool

Technical Specifications