JPEG 2000 120P Encoder/JPEG 2000 Decoder

Overview

The JPEG 2000 Broadcast family has been designed to respond to the various applications of the Broadcast markets. We guarantee perfect interoperability with every SD and HD standards in terms of frame rates and resolutions. Its modules provide, in a single FPGA, multi-channel operations representing a total of 240 full resolution progressive frames per second, real time.

Key Features

Up to 1 HD 120p channel or 2 HD 60p channels or 4 HD 30p / 50i / 59,9i / 60i channels
Visually lossless compression
Xilinx 7 Series FPGA (Zynq-7, Artix-7, Kintex-7, Virtex-7), Xilinx Virtex-6
Altera Arria V, Stratix IV and Stratix V
Function:

JPEG 2000 Encoder
JPEG 2000 Decoder

Max codestream bitrate; Lower bitrate supported; Bitrate can be shared unequally per channel: 1000 Mbps
Max pixel rate ; Lower pixel rate supported: 280 Mpixels/s
Max pixels per line; Lower pixels per line supported: 1920 pixels/line
Max bit depth per component ; Lower bit depth supported: 10 Bits/comp.
Latency:

Low Latency(2 + 1 frames)
Ultra-low Latency(<1 frame)

Color Space: YUV or RGB
Chrominance subsampling:

4:4:4 (Option)
4:2:2

Benefits

Full flexibility between

up to 4 simultaneous channels
1 channel up to 1080p, 120 fps

Visually Lossless
Single chip
Ultra Low Latency Option

Applications

Camera built-in recorder
Field recorder
Post-production video server
Contribution transceiver/receiver
Live event transmitter
SMPTE2022 1/2 (JPEG2000 wrapped in MPEG2-TS )
AVB

Technical Specifications

Availability

Now

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