JESD204B IP Core
Overview
JEDEC Standard No. 204B (JESD204B) describes a serialized interface between data converters and logic devices. It contains the information necessary to allow designers to implement logic devices which can communicate with other devices (converters) that are compliant with the standard. Lattice’s JESD204B 3G/5G IP Core offerings support both an Rx core (ADC to FPGA direction) and/or a Tx core (FPGA to DAC direction). The Rx and Tx cores can each be generated separately and with different parameters.
Key Features
- Subsets of JEDEC Standard No. 204B(JESD204B.01) July 2011
- Rx core performs lane alignment based on Subclass 0 and Subclass 1
- Rx core performs frame alignment detection / monitoring and octet reconstruction
- Rx core performs user-enabled descrambling
- Rx core recovers link configuration parameters during initial lane synchronization and compares them to user selected parameters to generate a configuration mismatch error
- Tx core performs user-enabled scrambling
- Tx core generates initial lane alignment sequence
- Tx core performs alignment character generation
- Tx core sources link configuration data with user selected parameter values during initial lane synchronization Sequence
- 16 bit(3G) or 32 bit(5G) fabric interface per channel for low core frequency
- One-shot frame/multi-frame boundary flags with one clock ahead of data make users easy to control the transition of the state machines for framer / de-framer
Block Diagram
Technical Specifications
Related IPs
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- BCH Encoder/Decoder IP Core
- DDR-I/II/III CONTROLLER IP CORE
- Vector Graphics IP core supporting OpenVG1.1 subset
- 10G/25GBASE-R PCS+KR4 FEC IP Core
- ARINC818 controller Transmitter and Receiver IP core