ITU-T G729A Voice Codec Hardware Accelerator

Overview

The growth in wireless communication systems, cellular mobile radio and VoIP technology has created the imperative need for bandwidth efficient, high speed quality voice coding algorithms. The ITU-T G.729 CS-ACELP is a high speech quality, low-bit rate (8kbps) codec that has been proposed to meet the voice compression requirements of a modern communication system.

However the real time SW implementation of a multi-channel ITU-T G.729 compliant voice codec in conventional DSP processors is prohibitive due to the intensive amount of signal processing power required by the algorithm. To overcome this limitation Noesis Technologies has developed a revolutionized, highly efficient hybrid architecture that implements real time multi-channel G729A voice coding and exhibits the best performance-silicon area ratio available in the industry. The ntG729 IP Core can be used as a coprocessor to any processor type and can save significant computing resources for the main processor by efficiently executing the computationally intensive speech coding G729A algorithmic operations.

Key Features

  • Voice codec capable of multi-channel 8kbps voice compression based on ITU-T G729A standard.
  • Selective Channel initialization.
  • AMBA bus support for easy SoC integration.
  • Best performance/silicon area ratio available in the industry.
  • Fully synchronous design, using single clock.
  • Portable to any FPGA/ASIC technology.

Benefits

  • The ntG729 hardware accelerator when compared with a software implementation of ITU-T G729A algorithm on high-end processors, presents impressive competitive advantages:
    • Outperforms by a factor of two by supporting twice as many voice channels.
    • It requires only half the gate count thus increasing power efficiency and reducing costs.
    • It presents an overall performance/silicon area ratio four times better than any high-end processor of the market.

Block Diagram

ITU-T G729A Voice Codec Hardware Accelerator Block Diagram

Deliverables

  • Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
  • VHDL or Verilog test benches and example configuration files.
  • C++ model.
  • Comprehensive technical documentation.
  • Technical support.

Technical Specifications

Foundry, Node
UMC
Maturity
Silicon Proven
Availability
Now
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Semiconductor IP