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Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP

Overview

Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively. The hard IP provides the Avalon® Streaming (Avalon-ST) interface and can be configured for either Rootport (RP) or Endpoint (EP) modes.

Complementary soft IPs are available for single root I/O virtualization (SR-IOV) support and bridging to an Avalon Memory Mapped interface (Avalon-MM) with DMA functionality.

Standards & Specifications Compliance

Intel Arria 10 PCIe Hard IP has successfully passed PCI-SIG compliance testing.

Key Features

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
  • Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Native Endpoints in Intel® Arria® 10 devices.
  • Support for ×1, ×2, and ×4 configurations with Gen1 or Gen2 lane rates for Native Endpoints in Intel® Cyclone® 10 GX devices.
  • Dedicated 16 KB receive buffer.
  • Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.
  • Example designs demonstrating parameterization, design modules, and connectivity.
  • Extended credit allocation settings to better optimize the RX buffer space based on application type.
  • Support for multiple packets per cycle with the 256 bit Avalon ST interface.
  • Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
  • Support for Separate Reference Clock No Spread Spectrum (SRNS) architecture.

Block Diagram

Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP Block Diagram

Technical Specifications

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