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Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core

Overview

Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet Intel® FPGA IP core is compliant with the IEEE 802.3ba-2010 standard, it includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block. It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Intel® Stratix® and Intel® Arria® FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules.

The IP core is designed to the IEEE 802.3ba-2010 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets. All Low Latency 100G Ethernet Intel® FPGA IP core variations include full duplex MAC and PHY components.

For a detailed specification of the Ethernet protocol, refer to the IEEE 802.3ba-2010 High-Speed Ethernet Standard.

Key Features

  • PHY features:
    • Soft PCS logic that interfaces seamlessly to Intel® Stratix® 10 FPGA 25.78125 Gbps serial transceivers
    • CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps
    • Optional Reed-Solomon forward error correction - RS(528,514) FEC
    • Support for Auto-Negotiation/Link Training (AN/LT) protocol
  • Frame structure control features:
    • Support for jumbo packets
    • TX and RX cyclic rredundancy check (CRC) pass-through control
    • Optional TX CRC generation and insertion
    • RX and TX preamble pass-through options for applications that require proprietary transfer of user management information
    • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length
  • Frame monitoring and statistics:
    • RX CRC checking and error reporting
    • Optional RX strict SFD checking per IEEE specification
    • RX malformed packet checking per IEEE specification
    • Received control frame type indication
    • Optional statistics counters
    • Optional fault signaling: reports local fault and generates remote fault (IEEE 802.3ba-2012 Ethernet Standard, Clause 66)
  • Flow control:
    • Optional Ethernet flow control operation using the pause registers or pause interface (IEEE 802.3, Clause 31)
    • Optional priority-based flow control that uses the pause registers for fine control (IEEE Standard 802.1Qbb-2011, Amendment 17)
    • Pause frame filtering control
  • Debug and testability features:
    • Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing
    • TX error insertion capability supports test and debug
    • Optional access to Intel® FPGA Debug Master Endpoint (ADME) for debugging or monitoring PHY signal integrity
  • User system interfaces:
    • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
    • Avalon-ST datapath interface connects to client logic with the start of frame in the most significant byte (MSB). The interface data width of 512 bits ensures the data rate despite this RX client interface SOP alignment and RX and TX preamble passthrough option
    • Hardware and software reset control
  • For a detailed specification of the Ethernet protocol, refer to the IEEE 802.3ba-2010 High-Speed Ethernet Standard.

Block Diagram

Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core Block Diagram

Technical Specifications

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