IEEE 1914.3 RoE Structure Agnostic Mapper/Demapper

Overview

Comcores Radio Over Ethernet Structure Agnostic Mapper/Demapper IP core is a silicon agnostic implementation of the structure agnostic mapping method described in the IEEE 1914.3 standard. The RoE IP-core takes multiple streams of CPRI data and map these into one or several 10G/25G Ethernet data streams and vice versa. The RoE IP core does as well allow for local injection and retraction of Ethernet traffic.

The RoE IP core allows easy configuration for various synchronization methods and works with CPRI in both slave and master mode. The RoE IP core has been successfully tested in HW and at system level.

Key Features

  • Delivers Performance
    • Complies with IEEE 1914.3 standard
    • Supports multiple streams of CPRI and Ethernet
    • Complies with CPRI 7.0 standard
    • Configurable for many operating modes
    • CPRI Line Rate speed from 614.4 – 24330.24 Mbps (only limited by HW)
    • Ethernet Line rates supported for both 10G and 25G
    • IEEE 1588 supported
    • Time of Day (ToD) supported
  • Easy to Use
    • HW demonstration setup available
    • Interfacing to all CPRI variants
    • CPRI SerDes interface supports both 8B 10B and 64B 66B
    • MAC interface through a 64 bit XGMII or Avalon Streaming
    • CPU interface through a 32 bit AXI4-Lite, APB or Avalon interface
  • Silicon Agnostic
    • Designed in VHDL and targeting both ASICs and FPGAs

Block Diagram

IEEE 1914.3 RoE Structure Agnostic Mapper/Demapper Block Diagram

Applications

  • Radio Designs
    • Enables Ethernet as a connectivity option for Radio’s
    • Used with designs where customer has own proprietary CPRI
  • Baseband designs
    • Enables Ethernet as a fronthaul option
    • Easy integration with legacy CPRI
  • Test
    • Fast track testing RoE implmentations
    • Many test options available in core

Deliverables

  • The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
    • Solid documentation, including User Manual and Release Note
    • Simulation Environment, including Simple Testbed, Test case, Test Script
    • Timing Constraints in Synopsys SDC format
    • Access to support system and direct support from Comcores Engineers
    • Synopsys Lint and CDC

Technical Specifications

Maturity
Mature
Availability
Available
×
Semiconductor IP