I2C Master Serial Interface Controller

Overview

The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC technologies.

Key Features

  • I2C-compatible interface
  • AMBA AXI4-Lite bus
  • Standard and custom data rates
  • Configurable setup/hold times
  • Multi-master support
  • Clock strechting support
  • Programmable SDA/SCL input filter
  • Automatic Start, Stop, Repeated Start, Acknowledge support
  • 7 and 10 bit addressing format support
  • Maskable interrupts
  • Dedicated upstream and downstream DMA interface
  • Fully synthesizable synchronous design with positive edge clocking
  • DFT ready

Benefits

  • Synthesizable RTL Verilog source code
  • Technology independent IP Core
  • Suitable for FPGA and ASIC
  • Silicon and FPGA proven
  • Easy SoC integration
  • Full implementation and maintenance support with individual approach
  • Flexible licensing scheme

Block Diagram

I2C Master Serial Interface Controller Block Diagram

Deliverables

  • Verilog RTL source code
  • Verification suite
  • Datasheet and integration guide
  • C-header file
  • Constraints
  • Technical support

Technical Specifications

Availability
Now
UMC
Silicon Proven: 130nm
×
Semiconductor IP